All-digital RF signal generation using delta-sigma modulation for mobile communication terminals

In the software defined radio context, a digital transmitter based on ΔΣ modulation is proposed. Its architecture is built around two oversampled 3rd-order lowpass digital ΔΣ modulators that provide a multiplexed high-speed 1-bit data stream directly coding the RF signal in the digital domain. The output stream can then be fed to an efficient switching-mode power amplifier.The UMTS standard has been taken as an application example and a digital RF signal generator providing the 1-bit output stream at 7.8Gs/s has been designed in a 90nm CMOS technology. Redundant arithmetic with complementary signal paths, non-exact output quantization and anticipated output evaluation have been implemented to reach the high sampling rate. 3-phase differential dynamic logic clocked by a DLL has been used at the circuit level.The fabricated prototype transmitter IC demonstrates full functionality up to a 4GHz main clock frequency, reaching a maximum bandwidth of 50MHz at 1GHz center frequency with a 3.1dBm peak output power. When using the first image band, the transmit band can be moved up to 3 GHz. With a 2.6GHz main clock frequency and 5MHz WCDMA modulated channel at a carrier frequency of 650MHz, a channel output power of -3.9dBm and 53.6dB of ACPR are obtained. With the same settings, a channel output power of -15.8dBm and an ACPR of 44.3dB is reached in the 1.95GHz image band, which fulfills minimum UMTS requirements. The chip active area is 0.15mm² and its power consumption is 69mW for a 2.6GHz operating clock frequency.Dans le cadre de la radio logicielle, un transmetteur numérique, basé sur la modulation ΔΣ, est proposé. Son architecture est construite autour de deux modulateurs ΔΣ passe-bas suréchantillonnés du 3ème ordre qui fournissent un signal multiplexé sur 1 bit à haute cadence, qui code directement le signal RF dans le domaine numérique. La séquence de sortie peut ensuite être appliquée à l'entrée d'un amplificateur de puissance commuté ayant une bonne efficacité.Le standard UMTS a été choisi comme exemple d'application et un générateur de signaux RF 1 bit à 7,8Géch/s a été réalisé dans une technologie 90nm CMOS. Une arithmétique redondante comprenant des signaux complémentaires, une quantification de sortie non exacte et une évaluation anticipée de la sortie ont été implémentées pour parvenir à la cadence désirée. Une logique dynamique différentielle sur 3 phases d'horloge, générées par une DLL, a été utilisée au niveau circuit.Le circuit intégré du transmetteur prototype démontre une fonctionnalité complète jusqu'à une fréquence d'horloge de 4GHz, permettant ainsi d'atteindre une bande passante de 50MHz autour d'une fréquence porteuse de 1GHz. Si la bande image est utilisée, la fréquence d'émission peut être déplacée jusqu'à 3GHz. Avec une fréquence d'horloge de 2,6GHz et un canal WCDMA de 5MHz modulé autour d'une fréquence porteuse à 650MHz, 53,6dB d'ACLR sont obtenus pour une puissance de canal en sortie de -3,9dBm. Pour la bande image (1,95GHz), l'ACPR est de 44,3dB pour une puissance maximale du canal en sortie de -15,8dBm, ce qui rentre dans les spécifications UMTS. L'aire active du circuit est de 0,15mm² et sa consommation de 69mW sous 1V à cette fréquence

Digital RF transmitter architectures exploiting FIRDACs in various configurations

International audienceThis paper discusses various ways to take advantage of semi-digital FIR filters (or FIRDACs) in highly digital RF and millimeter-wave transmitters. FIRDACs combine in a single block digital-to-analog conversion and filtering. When fed with 1-bit digital signals provided by digital delta-sigma modulators or other sources, the inherent linearity of 1 bit D-to-A converters is also preserved reducing significantly the sensitivity to component matching. Architectures using FIRDACs in base-band, IF or RF sections will be discussed, as well as opportunities for reconfiguration in highly advanced CMOS processes. Implementation examples in advanced technologies down to 28nm CMOS demonstrate the performance and scalability of these architectures

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

International audienceThis paper presents a complex delta-sigma modu-lator (CDSM) designed for integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta sigma modulator (DSM), complex delta sigma modulator (CDSM), finite impulse response (FIR), multi-standard coexistence, digital transmitter

Keyword Spotting System using Low-complexity Feature Extraction and Quantized LSTM

International audienceLong Short-Term Memory (LSTM) neural networks offer state-of-the-art results to compute sequential data and address applications like keyword spotting. Mel Frequency Cepstral Coefficients (MFCC) are the most common features used to train this neural network model. However, the complexity of MFCC coupled with highly optimized machine learning neural networks usually makes the MFCC feature extraction the most power-consuming block of the system. This paper presents a low complexity feature extraction method using a filter bank composed of 16 channels with a quality factor of 1.3 to compute a spectrogram. It shows that we can achieve an 89.45% accuracy on 12 classes of the Google Speech Command Dataset using an LSTM network of 64 hidden units with weights and activation quantized to 9 bits and inputs quantized to 8 bits

Distributed Artificial Intelligence Integrated Circuits For Ultra-Low-Power Smart Sensors

International audienceWireless sensor networks (WSN) could be defined as networks of autonomous devices that can sense and/or act on a physical or environmental conditions cooperatively. .To make these sensors smarter, Artificial Intelligence (AI) is used to process sensed data but also to solve challenges such as security, energy aware rooting, ect. This paper present a solution of using AI in the case of distributed sensors networks that aims to tackle these challenge

Slope-Based Event-Driven Feature Extraction For Cardiac Arrhythmia Classification

International audienceTo detect cardiovascular diseases (CVD), electrocardiogram (ECG) of a patient must be recorded and analyzed for a long period. For an effective diagnosis, the ECG recording system must automatically adapt to new patients. This paper presents a low-complexity artificial neural network that exclusively uses the consecutive slopes of ECG signal as inputs. These features are extracted using a level-crossing ADC and a simple TDC-based event-driven processing chain. The proposed clockless system can detect arrhythmias in ECG with 98.4% accuracy and reduce the ANN hardware complexity by more than half compared to recent literature. It is perfectly adapted to integrated wearable monitoring systems and shows good adaptability to new patients. Keywords-Artificial neural network (ANN), electrocardiogram (ECG), cardiac arrhythmia classification (CAC), event-driven, time-to-digital converter (TDC), levelcrossing AD

Antidictionary-Based Cardiac Arrhythmia Classification for Smart ECG Sensors

International audienceCardiovascular diseases can be detected early by analyzing the electrocardiogram of a patient using wearable systems. In the context of smart sensors, detecting arrhythmias with good accuracy and ultra-low power consumption is required for long-term monitoring. This paper presents a novel cardiac arrhythmia classification method based on antidictionaries. The features are sequences of consecutive slopes that are generated from event-driven processing of the input signal. The proposed system shows an average detection accuracy of 98% while offering an ultra-low complexity. This antidictionary-based method is also particularly suited to imbalanced datasets since the antidictionaries are created exclusively from heartbeats classified as normal beats

Analog Duty Cycle Controller Using Backgate Body Biasing For 5G Millimeter Wave Applications

POSTERInternational audienceThis work presents the first 21-43 GHz CMOS analog Duty Cycle Controller (DCC) implemented in 28 nm FDSOI. The main application is millimeter wave mixers with CMOS digital signals. The proposed circuit corrects the input duty cycle with a negative feedback analog loop. Observability of the duty cycle is made through a passive low pass filter and the control is achieved by modifying the rise and fall time of the input clock signal, via backgate biasing of an inverter chain. The circuit has been validated by post layout, Monte-Carlo and corner simulations. At 28 GHz, the duty cycle correction range varies from 40 % to 55 %, and the additional power consumption introduced by the correction loop is frequency independent and is equal to 0.6 mW